Modelling Digital Logic in SDL

The specification of digital logic in SDL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic

Copyright © 2003, Object Management Group

The material in this document details an Object Management Group specification in accordance with the terms, conditions and notices set forth below. This document does not represent a commitment to implement any portion of this specification in any company's products. The information contained in this document is subject to change without notice. LICENSES The companies listed above have granted to the Object Management Group, Inc. (OMG) a nonexclusive, royalty-free, pai

Applying SAMSTAG to the B-ISDN protocol SSCOP

The test generation method SAMSTAG (SDL and MSC based test case generation) has been applied successfully to the B-ISDN ATM Adaption Layer protocol SSCOP (Service Specific Connection Oriented Protocol). For approximately 70% of the identified test purposes complete TTCN test cases have been generated automatically. In this paper we describe the experiment, discuss the results and explain how further improvements of the test generation process can be achieved. Keywords Test case generation, protocol validation, SDL, MSC, TTCN, B-ISDN ATM 1 INTRODUCTION From 1991 to 1993 Swiss PTT promoted a project at the University of Berne which was aimed at suporting the conformance testing process. One objective was the development and implementation of a method for the automatic generation of abstract test cases in TTCN format based on SDL system specifications and MSC test purposes. As a main result of this project we developed the SAMSTAG method and implemented the SAMSTAG tool [Grabowski, 19..

On the Influence of Semantic Constraints on the Code Generation from Estelle Specifications

Implementations automatically derived from formal descriptions often do not fulfill the performance requirements of real-life applications. There are several reasons for this. In the paper, we address two of these issues for the FDT Estelle. The first issue has to do with the impact of the Estelle semantics on the code generation. We show that a performance gain can be achieved, if the module attributes are applied with care. The second issue relates to the implementation model applied for the automatic code generation. We discuss how the activity thread model, a technique known from manual protocol implementation, can be applied to automatically derive efficient implementations from Estelle specifications. The activity thread model reduces the overhead for process and memory management. In the paper, we analyze the prerequisites to apply the model and present measurements comparing the performance achievable with the technique. The measurements are given for different implementations of XTP and the XDT protocol